代码搜索:dataIn

找到约 2,888 项符合「dataIn」的源代码

代码结果 2,888
www.eeworm.com/read/159159/10687900

v muart.v

//`include "ClkUNIT.v" //`include "TxUNIT.v" //`include "RxUNIT.v" module MUART(SysClk, Reset, CS_N, RD_N, WR_N, TxD, RxD, IntRx_N, IntTx_N, Addr, DataIn, DataOut); input SysClk;
www.eeworm.com/read/451035/7473317

vhd shiftreg2to1.vhd

library ieee; use ieee.std_logic_1164.all; entity shiftreg2to1 is port(clk,cr:in std_logic; datain:in std_logic_vector(0 to 1); dataout:out std_logic); end shiftreg2to1; architecture
www.eeworm.com/read/17540/737638

cpld

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MEALY1 IS PORT ( CLK ,DATAIN,RESET : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); END MEALY1; ARCHITECTURE behav OF MEALY1
www.eeworm.com/read/287040/8729292

bak datacnl.v.bak

module datacnl( clk, rst, r_ram_rdb, r_ram_rab, r_req_in, s_ram_wdb, s_ram_wab, s_ram_wen, s_req_in, cmd, cmdack, addr, datain, dataout, start_send, sta
www.eeworm.com/read/424942/10390554

bak datacnl.v.bak

module datacnl( clk, rst, r_ram_rdb, r_ram_rab, r_req_in, s_ram_wdb, s_ram_wab, s_ram_wen, s_req_in, cmd, cmdack, addr, datain, dataout, start_send, sta
www.eeworm.com/read/353951/10402875

hier_info fifo_cntl.hier_info

|fifo_cntl empty => led[2].DATAIN btn[0] => btn_a.ACLR btn[0] => state.ACLR btn[0] => counter[11].ACLR btn[0] => counter[10].ACLR btn[0] => counter[9].ACLR btn[0] => counter[8].ACLR btn[0] =>
www.eeworm.com/read/296373/8108689

vhd hdb.vhd

--加B部分 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity hdb is port(reset,clk:in std_logic; datain: in std_logic_vector(1 downto 0); dout: out std_
www.eeworm.com/read/480305/6672250

vhd mydecoder.vhd

library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity decoder is --实体说明 port(datain,clk,clr:IN std_logic; dataout:OUT std_logi
www.eeworm.com/read/262703/11394604

vhd dds.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dds is Port ( clk : in STD_LOGIC; dds_datain: in std_logic_vector(31 d
www.eeworm.com/read/287040/8729282

v datacnl_mask.v

module datacnl_mask( clk, rst, r_ram_rdb, r_ram_rab, r_req_in, s_ram_wdb, s_ram_wab, s_ram_wen, s_req_in, cmd, cmdack, addr, datain, dataout, start_send,