dds.vhd

VHDL编写的驱动DDS

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dds is
    Port ( clk : in  STD_LOGIC;
	   dds_datain: in std_logic_vector(31 downto 0);
	   dds_wclk: out std_logic;
	   dds_fqud: out std_logic;
	   dds_reset: out std_logic;
	   dir	: out std_logic_vector(1 downto 0);
	   oe	: out std_logic_vector(1 downto 0);
	   dds_data: out std_logic_vector( 7 downto 0);
	   div_clk: out std_logic);
		
end dds;

architecture Behavioral of dds is
	SIGNAL	count	: std_logic_vector(3 downto 0);
	SIGNAL  clkdiv  : std_logic;
	signal	data_reg: std_logic_vector(39 downto 0);
	signal 	stat:std_logic_vector(3 downto 0);
begin
	dir <="00";
	oe  <="00";
	PROCESS (clk)------------------------------分频
	BEGIN
		IF (clk' event AND clk='1') THEN
		
					
			IF (count = "1111") THEN
					
				count  <= "0000";
				clkdiv <=NOT clkdiv;
					
			ELSE
			
				count <= count + 1;
				
			END IF;
			
		END IF;
		
	END PROCESS;

------------------------------------------------------------------------------------
	PROCESS(clkdiv)
		BEGIN
		IF clkdiv'EVENT AND clkdiv='1' THEN	
				data_reg(39 DOWNTO 32)<="00000000";
				data_reg(31 DOWNTO 0)<=dds_datain;
			--写频率----------------------------------------------------------------
				IF STAT="0000" THEN --0
				
					dds_data<=data_reg(39 DOWNTO 32);--相位
					STAT<="0001";
				ELSIF STAT="0001" THEN--1
					dds_wclk<='1';
					STAT<="0010";
					
				ELSIF STAT="0010" THEN--2
					dds_data<=data_reg(31 DOWNTO 24);--频率1
					dds_wclk<='0';
					STAT<="0011";
				ELSIF STAT="0011" THEN--3
					dds_wclk<='1';
					STAT<="0100";
				ELSIF STAT="0100" THEN--4
					dds_data<=data_reg(23 DOWNTO 16);--频率2
					dds_wclk<='0';
					STAT<="0101";
				ELSIF STAT="0101" THEN--5
					dds_wclk<='1';
					STAT<="0110";
				ELSIF STAT="0110" THEN--6
					dds_data<=data_reg(15 DOWNTO 8);--频率3
					dds_wclk<='0';
					STAT<="0111";
				ELSIF STAT="0111" THEN--7
					dds_wclk<='1';
					STAT<="1000";
				ELSIF STAT="1000" THEN--8
					dds_data<=data_reg(7 DOWNTO 0);--频率4
					dds_wclk<='0';
					STAT<="1001";
				ELSIF STAT="1001" THEN--9
					dds_wclk<='1';
					STAT<="1010";
				ELSIF STAT="1010" THEN--10
					dds_wclk<='0';
					dds_fqud<='1';
					STAT<="1011";
				ELSIF STAT="1011" THEN--11
					dds_fqud<='0';
					STAT<="0000";			
				END IF;
		END IF;
	END PROCESS;
	------------------------------------------------------------------

div_clk<=clkdiv;
end Behavioral;