shiftreg2to1.vhd

红外4PPM解码的源程序

library ieee;
use ieee.std_logic_1164.all;
entity shiftreg2to1 is
port(clk,cr:in std_logic;
     datain:in std_logic_vector(0 to 1);
     dataout:out std_logic);
end shiftreg2to1;
architecture behavior of shiftreg2to1 is
signal reg2:std_logic_vector(0 to 1);
signal count:integer range 0 to 2;
begin
process(clk)
begin
if(clk'event and clk='1') then
count<=count+1;
if(count=2)then
count<=0;
end if;
end if;
end process;
process(clk,cr)
begin
if(cr='0') then
reg2<=( others=>'0' );
elsif(clk'event and clk='1') then
if count>0 then
reg2(1)<=reg2(0);
elsif(count=0) then
reg2<=datain;
end if;
end if;
dataout<=reg2(1);
end process;
end behavior;