hdb.vhd

来自「hDB3的编解码模块 是在maxplusII 下验证过的 并且下到片子中都正」· VHDL 代码 · 共 58 行

--加B部分
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity hdb is
port(reset,clk:in std_logic;
     datain: in std_logic_vector(1 downto 0);
     dout: out std_logic_vector(1 downto 0));
end;

architecture rtl of hdb is
signal D1,D0:std_logic_vector(3 downto 0);
signal flag,even:integer range 0 to 1;
begin
process(clk,datain)is
begin   
if(clk='1' and clk'event)then
  D1(3)<=datain(1);
  D0(3)<=datain(0);
  D1(2 downto 0)<=D1(3 downto 1);
  D0(2 downto 0)<=D0(3 downto 1);
end if;
end process;

process(reset,clk,D1,D0) is
begin
if reset='0' then
 flag<=0;
 even<=0;
elsif(clk='1' and clk'event)then
 if (D1(3)='1' and D0(3)='1')then
    flag<=1;
 else flag<=0;
 end if;

 if(D1(0)='0' and D0(0)='1')then
   even<=even+1;
 elsif(D1(0)='1' and D0(0)='1')then
   even<=0;
 end if;
end if;
end process;

process(reset,clk) is
begin
if reset='0' then dout<="00";
elsif(clk='1' and clk'event) then
 if(flag=0 and even=0 and (D1(3)='1' and D0(3)='1')) then
   dout<="10";
 else dout<=D1(0)&D0(0);
 end if;
end if;
end process; 
end;