hdb3c.vhd

来自「hDB3的编解码模块 是在maxplusII 下验证过的 并且下到片子中都正」· VHDL 代码 · 共 36 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity hdb3c is
port(reset,clk: in std_logic;
     datain: in std_logic_vector(1 downto 0);
     dout: out std_logic_vector(1 downto 0));
end entity;

architecture rtl of hdb3c is
signal even:std_logic;
begin
process(reset,clk,datain)is
begin
if reset='0' then
  even<='0';
  dout<="00";
elsif(clk='1' and clk'event)then
  if datain="11" then
    if even='1' then
       dout<="11";   --负电平1
    else dout<="01"; --正电平1
    end if;
  elsif(datain="01" or datain="10") then
    if even='1' then even<='0';
                     dout<="01";
    else even<='1';
         dout<="11";
    end if;
  else  dout<="00";
  end if;
end if;
end process;
end;