mydecoder.vhd

VHDL编写的基于FPGA的4-8交织器代码

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity decoder is			--实体说明
port(datain,clk,clr:IN std_logic;
     dataout:OUT std_logic_vector(7 downto 0);		--输入输出端口
     --re,we:IN std_logic;	--片内ram的读使能和写使能信号	
     clkout:INOUT std_logic;
     wraddress,rdaddress:INOUT std_logic_vector(5 downto 0);
      test : out std_logic_vector(15 downto 0));--测试端口
end decoder;

architecture d1 of decoder is		--结构说明
signal clk_ram,data:std_logic;--ram的读写时钟信号以及输出串行数据
signal m:std_logic_vector(7 downto 0):="00000000";--串并转化用的寄存单元
signal dataout1:std_logic_vector(7 downto 0):="00000000";--解织器输出8位并行信号
signal addr:std_logic:='0';--片内ram的读写地址
signal number:std_logic_vector(5 downto 0):="000000";--计数器输出
signal memory12:std_logic_vector(63 downto 0);--ram大小为8*8bit

type ram is array(0 to 1) of std_logic_vector(7 downto 0);--片内ram有两个byte单元


begin

	clk_ram<=NOT clk;		--双口ram的时钟信号
    test(5 downto 0)<= number; 
  --  test(13 downto 6)<=CONV_STD_LOGIC_VECTOR(memory(7 downto 0));   
    test(15 downto 14)<="00";

	process(clk)

 
	begin
--		if(clk'event and clk='1') then	--实现计数器
			if(clr='1') then
				number <="000000";
			elsif(clk'event and clk='1') then
				if(number="111111") then
					number<="000000";
				else
					number<=number+1;
				end if;
			end if;
--		end if;		--计数器实现完毕
		
		wraddress<=number;--产生读地址
		rdaddress(5)<=NOT number(5);--产生写地址
		rdaddress(4)<=number(1);
		rdaddress(3)<=number(0);
		rdaddress(2)<=number(4);
		rdaddress(1)<=number(3);
		rdaddress(0)<=number(2);

  end process;
      
	process(clk_ram)	
	variable memory:std_logic_vector(63 downto 0);--ram大小为8*8bit
	begin
			if(clr='1') then
				data<='0';
		elsif(clk_ram'event and clk_ram='1') then		--实现双口ram，同时进行读写操作
	--		else
				memory(conv_integer(wraddress)):=datain;
				data<=memory(conv_integer(rdaddress));
			end if;				--ram实现完毕,得到串行解交织码
--		end if;
        test(13 downto 6)<=memory(7 downto 0); 
 --       memory12 <= CONV_STD_LOGIC_VECTOR(memory) ;
  end process;
  
  process(clk_ram)
  variable tmp:std_logic_vector(2 downto 0):="000";
  begin
			if(clr='0') then
				tmp:="000";
				m<="00000000";
		elsif(clk_ram'event and clk_ram='1') then		--8分频得到clkout以及串并转化	
			if(tmp="111") then
					dataout1<=m;
					tmp:="000";
			else
				m(conv_integer(tmp))<=data;--如果是从高位开始读，此处要改为m(7-conv_integer(tmp))<=data
				tmp:=tmp+1;
			end if;
		end if;	
		clkout<=tmp(2);
	end process;
	
	process(clkout)
	variable ram1:ram;
	begin
			if(clr='1') then
				dataout<="00000000";
				addr<='0';
		elsif(clkout'event and clkout='1') then				--片内ram实现(2*8bit)
			addr<=NOT addr;						--addr二进制变化
	--		else
				ram1(conv_integer(addr)):=dataout1;			
				dataout<=ram1(conv_integer(NOT addr));
			end if;
	--	end if;								
	end process;
	
end d1;