fifo_cntl.hier_info

Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序

|fifo_cntl
empty => led[2].DATAIN
btn[0] => btn_a.ACLR
btn[0] => state.ACLR
btn[0] => counter[11].ACLR
btn[0] => counter[10].ACLR
btn[0] => counter[9].ACLR
btn[0] => counter[8].ACLR
btn[0] => counter[7].ACLR
btn[0] => counter[6].ACLR
btn[0] => counter[5].ACLR
btn[0] => counter[4].ACLR
btn[0] => counter[3].ACLR
btn[0] => counter[2].ACLR
btn[0] => counter[1].ACLR
btn[0] => counter[0].ACLR
btn[0] => slwr~reg0.PRESET
btn[0] => o_data[15]~reg0.PRESET
btn[0] => o_data[14]~reg0.ACLR
btn[0] => o_data[13]~reg0.PRESET
btn[0] => o_data[12]~reg0.ACLR
btn[0] => o_data[11]~reg0.PRESET
btn[0] => o_data[10]~reg0.ACLR
btn[0] => o_data[9]~reg0.PRESET
btn[0] => o_data[8]~reg0.ACLR
btn[0] => o_data[7]~reg0.PRESET
btn[0] => o_data[6]~reg0.ACLR
btn[0] => o_data[5]~reg0.PRESET
btn[0] => o_data[4]~reg0.ACLR
btn[0] => o_data[3]~reg0.PRESET
btn[0] => o_data[2]~reg0.ACLR
btn[0] => o_data[1]~reg0.PRESET
btn[0] => o_data[0]~reg0.ACLR
btn[0] => channel[3].ENA
btn[0] => channel[2].ENA
btn[0] => channel[1].ENA
btn[0] => channel[0].ENA
btn[1] => btn_a.DATAIN
full => led[0].DATAIN
full => slwr~0.DATAB
full => channel~7.OUTPUTSELECT
full => channel~6.OUTPUTSELECT
full => channel~5.OUTPUTSELECT
full => channel~4.OUTPUTSELECT
full => counter~23.OUTPUTSELECT
full => counter~22.OUTPUTSELECT
full => counter~21.OUTPUTSELECT
full => counter~20.OUTPUTSELECT
full => counter~19.OUTPUTSELECT
full => counter~18.OUTPUTSELECT
full => counter~17.OUTPUTSELECT
full => counter~16.OUTPUTSELECT
full => counter~15.OUTPUTSELECT
full => counter~14.OUTPUTSELECT
full => counter~13.OUTPUTSELECT
full => counter~12.OUTPUTSELECT
full => o_data~15.OUTPUTSELECT
full => o_data~14.OUTPUTSELECT
full => o_data~13.OUTPUTSELECT
full => o_data~12.OUTPUTSELECT
full => o_data~11.OUTPUTSELECT
full => o_data~10.OUTPUTSELECT
full => o_data~9.OUTPUTSELECT
full => o_data~8.OUTPUTSELECT
full => o_data~7.OUTPUTSELECT
full => o_data~6.OUTPUTSELECT
full => o_data~5.OUTPUTSELECT
full => o_data~4.OUTPUTSELECT
full => o_data~3.OUTPUTSELECT
full => o_data~2.OUTPUTSELECT
full => o_data~1.OUTPUTSELECT
full => o_data~0.OUTPUTSELECT
clk => num[4].CLK
clk => num[3].CLK
clk => num[2].CLK
clk => num[1].CLK
clk => num[0].CLK
clk => clk_25M.CLK
o_data[0] <= o_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
o_data[1] <= o_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
o_data[2] <= o_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
o_data[3] <= o_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
o_data[4] <= o_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
o_data[5] <= o_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
o_data[6] <= o_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
o_data[7] <= o_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
o_data[8] <= o_data[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
o_data[9] <= o_data[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
o_data[10] <= o_data[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
o_data[11] <= o_data[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
o_data[12] <= o_data[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
o_data[13] <= o_data[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
o_data[14] <= o_data[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
o_data[15] <= o_data[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fifoadr[0] <= <GND>
fifoadr[1] <= <GND>
pktend <= <VCC>
slwr <= slwr~reg0.DB_MAX_OUTPUT_PORT_TYPE
led[0] <= full.DB_MAX_OUTPUT_PORT_TYPE
led[1] <= slwr~reg0.DB_MAX_OUTPUT_PORT_TYPE
led[2] <= empty.DB_MAX_OUTPUT_PORT_TYPE
ifclk <= clk_25M.DB_MAX_OUTPUT_PORT_TYPE
slcs <= <VCC>