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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mux3vht is
generic(
create_rpm : integer := 0;
port_width : integer := 8
);
port(
d0 : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity vfft32_bflyw_j_v2_0 is
generic(
bfly_width : integer := 12;
diff_with_0_scaling: integer := 1
);
port(
x0r
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity kdcm_v2_0 is
generic(
b_signed : integer := 1;
constant_datab : integer := 3;
constant_widthb : integer := 4;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity vfft32_butterfly_v2_0 is
generic(
b : integer := 12;
w_width : integer := 12;
memory_architecture: i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity and_a_notb_v2 is
generic(
c_enable_rlocs : integer := 1
);
port(
a_in : in vl_logic;
b_in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity and_fd_v4 is
generic(
init_val : string := "0";
c_enable_rlocs : integer := 1;
no : integer := 0;
xstdemo_vlog_prj.npl
JDF F
// Created by Project Navigator ver 1.0
PROJECT XSTDemo_Vlog_Prj
DESIGN xstdemo_vlog_prj Normal
DEVFAM virtex2
DEVFAMTIME 1038040485
DEVICE xc2v40
DEVICETIME 0
DEVPKG cs144
DEVPKGTIME 0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mvbif is
port(
clk : in vl_logic;
rst : in vl_logic;
cs_cpu_n : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity Lf_delay is
generic(
L_t : integer := 16
);
port(
clk : in vl_logic;
reset :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ADPLL is
generic(
cnt_size : integer := 4;
del : integer := 1;
duty : integer := 2;