_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity vfft32_butterfly_v2_0 is
    generic(
        b               : integer := 12;
        w_width         : integer := 12;
        memory_architecture: integer := 1;
        ainit_val       : string  := "0000000";
        sinit_val       : string  := "0000000";
        max_complex_mult_latency: integer := 6;
        max_bfly_latency: integer := 7;
        delay_upper_arm_by: integer := 6;
        latency_thro_mult_vgen: integer := 1;
        latency_thro_comp_mult: integer := 1;
        upperarm_diff0  : integer := 0
    );
    port(
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        start_bf        : in     vl_logic;
        start           : in     vl_logic;
        reset           : in     vl_logic;
        scale_factor    : in     vl_logic_vector(1 downto 0);
        x0r             : in     vl_logic_vector;
        x0i             : in     vl_logic_vector;
        x1r             : in     vl_logic_vector;
        x1i             : in     vl_logic_vector;
        done            : in     vl_logic;
        y0r             : out    vl_logic_vector;
        y0i             : out    vl_logic_vector;
        y1r             : out    vl_logic_vector;
        y1i             : out    vl_logic_vector;
        ovflo           : out    vl_logic;
        wi              : in     vl_logic_vector;
        wr              : in     vl_logic_vector
    );
end vfft32_butterfly_v2_0;