_primary.vhd

来自「MVBC VHDL代码．．实现多功能车辆总线的通信」· VHDL 代码 · 共 27 行

library verilog;
use verilog.vl_types.all;
entity mvbif is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        cs_cpu_n        : in     vl_logic;
        int_mvbc0_n     : in     vl_logic;
        int_mvbc1_n     : in     vl_logic;
        wr_cpu_n        : in     vl_logic;
        oe_cpu_n        : in     vl_logic;
        addr_cpu        : in     vl_logic_vector(23 downto 0);
        rdy2mvbc_n      : in     vl_logic;
        cs              : in     vl_logic_vector(6 downto 0);
        addr_mvbc       : out    vl_logic_vector(23 downto 0);
        rdy2cpu_n       : out    vl_logic;
        rst_mvbc        : out    vl_logic;
        wr_mvbc_n       : out    vl_logic;
        rd_mvbc_n       : out    vl_logic;
        cs_mvbc_n       : out    vl_logic;
        int_cpu0_n      : out    vl_logic;
        int_cpu1_n      : out    vl_logic;
        jteg_en         : out    vl_logic;
        spare0          : out    vl_logic
    );
end mvbif;