_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity mux3vht is
    generic(
        create_rpm      : integer := 0;
        port_width      : integer := 8
    );
    port(
        d0              : in     vl_logic_vector;
        d1              : in     vl_logic_vector;
        d2              : in     vl_logic_vector;
        s0              : in     vl_logic;
        s1              : in     vl_logic;
        o               : out    vl_logic_vector
    );
end mux3vht;