_primary.vhd

来自「将数据延时5拍,可在modelsim中仿真。」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity Lf_delay is
    generic(
        L_t             : integer := 16
    );
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        r               : in     vl_logic_vector;
        r_delay5        : out    vl_logic_vector
    );
end Lf_delay;