_primary.vhd

来自「verilog ADPLL file with testbench.v」· VHDL 代码 · 共 18 行

library verilog;
use verilog.vl_types.all;
entity ADPLL is
    generic(
        cnt_size        : integer := 4;
        del             : integer := 1;
        duty            : integer := 2;
        cycle_time      : integer := 200
    );
    port(
        clk             : in     vl_logic;
        clk_in          : in     vl_logic;
        rst             : in     vl_logic;
        limit           : in     vl_logic_vector;
        clk_out         : out    vl_logic
    );
end ADPLL;