xstdemo_vlog_prj.npl

Xilinx Ise 官方源代码盘 第四章

JDF F
// Created by Project Navigator ver 1.0
PROJECT XSTDemo_Vlog_Prj
DESIGN xstdemo_vlog_prj Normal
DEVFAM virtex2
DEVFAMTIME 1038040485
DEVICE xc2v40
DEVICETIME 0
DEVPKG cs144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
FLOW XST Verilog
FLOWTIME 1038041252
MODULE cnt_vlog.v
MODSTYLE cnt_vlog Normal
[Normal]
xilxSynthMaxFanout=xstvlg, virtex2, Verilog.t_synthesize, 1038040716, 100
_SynthOptEffort=xstvlg, virtex2, Verilog.t_synthesize, 1038040716, High
[STRATEGY-LIST]
Normal=True