代码搜索结果
找到约 10,000 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity shift_reg is
port(
shiftreg : out vl_logic_vector(4 downto 0);
clock : in vl_logic;
reset
t
function verilog_left_shift(val: Bit_Vector; n: integer)
return Bit_Vector is
variable result: Bit_Vector ( 0 to (val'length -1));
begin
result:=val;
if (val'length > n) then
for i in
sap_1_tb_settings.txt
[SETTINGS]
UUT_module%SAP_1%
TB_module%SAP_1_tb%
DSN_PATH%$DSN\src\TestBench%
OUTPUT_DIRECTORY%C:\My_Designs\sap1\src\TestBench%
STIMULUS%NO%
VECTORS_FILE%%
AWF_FILE%%
TB_FILE%SAP_1_TB.v%
MAC
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cla4 is
port(
p : in vl_logic_vector(3 downto 0);
g : in vl_logic_vector(3 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cpu_alu is
generic(
z_delay : real := 1.500000;
alu_delay : real := 4.500000
);
port(
alu_out
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cpu_clkg is
generic(
period : integer := 60
);
port(
fetch : out vl_logic;
clk2 :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity iir_filter is
port(
din : in vl_logic_vector(17 downto 0);
dout : out vl_logic_vector(17 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fir_top is
port(
din : in vl_logic_vector(11 downto 0);
dout : out vl_logic_vector(31 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fir_mac is
port(
a : in vl_logic_vector(11 downto 0);
b : in vl_logic_vector(11 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity asr_ram is
port(
din : in vl_logic_vector(11 downto 0);
dout : out vl_logic_vector(11 downto 0);