_primary.vhd

使用ＭＡＴＬＡＢ工具

library verilog;
use verilog.vl_types.all;
entity iir_filter is
    port(
        din             : in     vl_logic_vector(17 downto 0);
        dout            : out    vl_logic_vector(17 downto 0);
        fltsel          : in     vl_logic;
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        clk_1           : in     vl_logic;
        ce_1            : in     vl_logic;
        rstn            : in     vl_logic
    );
end iir_filter;