_primary.vhd

使用ＭＡＴＬＡＢ工具

library verilog;
use verilog.vl_types.all;
entity asr_ram is
    port(
        din             : in     vl_logic_vector(11 downto 0);
        dout            : out    vl_logic_vector(11 downto 0);
        clk             : in     vl_logic;
        wren            : in     vl_logic;
        waddr           : in     vl_logic_vector(7 downto 0);
        raddr           : in     vl_logic_vector(7 downto 0);
        oen             : in     vl_logic
    );
end asr_ram;