_primary.vhd

来自「这是一个Verilog HDL编写的RISC cpu的程序」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity cpu_alu is
    generic(
        z_delay         : real    := 1.500000;
        alu_delay       : real    := 4.500000
    );
    port(
        alu_out         : out    vl_logic_vector(15 downto 0);
        zero            : out    vl_logic;
        opcode          : in     vl_logic_vector(2 downto 0);
        data_in         : in     vl_logic_vector(15 downto 0);
        accum           : in     vl_logic_vector(15 downto 0);
        clk             : in     vl_logic
    );
end cpu_alu;