_primary.vhd

来自「这是一个Verilog HDL编写的RISC cpu的程序」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity firfilter_1 is
    port(
        clock           : in     vl_logic;
        reset           : in     vl_logic;
        x               : in     vl_logic_vector(7 downto 0);
        y               : out    vl_logic_vector(7 downto 0)
    );
end firfilter_1;