_primary.vhd

使用ＭＡＴＬＡＢ工具

library verilog;
use verilog.vl_types.all;
entity fir_top is
    port(
        din             : in     vl_logic_vector(11 downto 0);
        dout            : out    vl_logic_vector(31 downto 0);
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        rstn            : in     vl_logic
    );
end fir_top;