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將Verilog設計轉成VHDL設計的程式

function verilog_left_shift(val: Bit_Vector; n: integer)
	return Bit_Vector is
	variable result: Bit_Vector ( 0 to (val'length -1));
	begin
		result:=val;
		if (val'length > n) then
			for i in 0 to (val'length-1-n) loop
				result(i) := result(i+n);
			end loop;
			for i in 0 to n-1
				result(val'length-1) := 0;
			end loop;
		else
			for i in 0 to (val'length - 1) loop
				result(i) := 0;
			end loop;
		endif;
		return result;
end verilog_left_shift;

entity adder4 is
generic(WORD : signed_word_int := 32; MEMSIZE : signed_word_int := 16);
port(in2, in1 : in bit_vector(WORD - 1 downto 0);
     busl : in out bit_vector(11 downto 3);
     out : out bit_vector(15 downto 0));
end adder4;

arhitecture VL2VHDL of adder4 is
begin
process begin
   sum <= 0;
   zero <= sum;
   sum <= in1 + in2;
   sum <=  verilog_left_shift(in1 , 2);
   i <= 0;
   while i < 10 loop
      in1 <= i;
      i <= i + 1;
   end loop;
   case ir(15 downto 12) is
      when B"010" =>
         pc <= m(ir(12 downto 0));
      when 12 | 11 =>
         acc <= acc - m(ir(2 downto 0));
      when others =>
         while ir(1 downto 0) < 2 loop
            pc <= pc + 1;
         end loop;
   end case;
   if (acc < 0) then
      pc <= pc + 1;
   else
      loop
         pc <= pc + 2;
      end loop;
   endif;
   block (
      (in2'event and in2 = '1') or in1'event
   )
   begin
      process begin
      if GUARD then
         out <= out + 1;
      end if;
      wait on GUARD;
      end process;
   end block;
end process;
end VL2VHDL;