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library verilog; use verilog.vl_types.all; entity add3 is port( clk_i : in vl_logic; rst_i : in vl_logic; \in\ : in vl_logic_vect

library verilog; use verilog.vl_types.all; entity pll1 is port( inclock : in vl_logic; locked : out vl_logic; clock0 : out vl_logic;

library verilog; use verilog.vl_types.all; entity ddr_sdram is port( clk : in vl_logic; reset_n : in vl_logic; addr : in vl_logic

library verilog; use verilog.vl_types.all; entity EndFlagDecision is generic( S_WaitforCMPResValid: integer := 1; S_DotheComparation: integer := 2; S_IDLE : intege

library verilog; use verilog.vl_types.all; entity FIFO2 is port( clock : in vl_logic; data : in vl_logic_vector(31 downto 0); rdreq :

library verilog; use verilog.vl_types.all; entity multiplexer4_1 is port( sel : in vl_logic_vector(1 downto 0); a : in vl_logic; b

library verilog; use verilog.vl_types.all; entity decoder3_8 is port( reset : in vl_logic; clk : in vl_logic; d_in : in vl_logi

library verilog; use verilog.vl_types.all; entity encoder8_3 is port( reset : in vl_logic; clk : in vl_logic; d_in : in vl_logi

library verilog; use verilog.vl_types.all; entity sdr_sdram is port( CLK : in vl_logic; RESET_N : in vl_logic; ADDR : in vl_logic

library verilog; use verilog.vl_types.all; entity main_top is port( clk : in vl_logic; rst_n : in vl_logic; cmdack : in vl_logic;