_primary.vhd

一个RAM的测试仿真程序

library verilog;
use verilog.vl_types.all;
entity main_top is
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        cmdack          : in     vl_logic;
        dataout         : in     vl_logic_vector(15 downto 0);
        cmd             : out    vl_logic_vector(2 downto 0);
        addr            : out    vl_logic_vector(22 downto 0);
        datain          : out    vl_logic_vector(15 downto 0);
        dm              : out    vl_logic_vector(1 downto 0);
        toLED           : out    vl_logic_vector(3 downto 0)
    );
end main_top;