_primary.vhd

来自「一个RAM的测试仿真程序」· VHDL 代码 · 共 22 行

library verilog;
use verilog.vl_types.all;
entity Bwrite_s is
    generic(
        s0              : integer := 0;
        s1              : integer := 1;
        s2              : integer := 2;
        IDLE            : integer := 3
    );
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        Bwrite_CE       : in     vl_logic;
        cmdack          : in     vl_logic;
        addr            : out    vl_logic_vector(22 downto 0);
        datain          : out    vl_logic_vector(15 downto 0);
        cmd             : out    vl_logic_vector(2 downto 0);
        Bfinish_W       : out    vl_logic;
        dm              : out    vl_logic_vector(1 downto 0)
    );
end Bwrite_s;