_primary.vhd

来自「综合仿真程序」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity encoder8_3 is
    port(
        reset           : in     vl_logic;
        clk             : in     vl_logic;
        d_in            : in     vl_logic_vector(7 downto 0);
        d_out           : out    vl_logic_vector(2 downto 0)
    );
end encoder8_3;