_primary.vhd

来自「综合仿真程序」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity comparator_4 is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        a               : in     vl_logic_vector(3 downto 0);
        b               : in     vl_logic_vector(3 downto 0);
        alb             : out    vl_logic;
        agb             : out    vl_logic;
        aleb            : out    vl_logic;
        ageb            : out    vl_logic;
        aeb             : out    vl_logic;
        aneb            : out    vl_logic
    );
end comparator_4;