_primary.vhd

来自「综合仿真程序」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity multiplexer4_1 is
    port(
        sel             : in     vl_logic_vector(1 downto 0);
        a               : in     vl_logic;
        b               : in     vl_logic;
        c               : in     vl_logic;
        d               : in     vl_logic;
        mux_out         : out    vl_logic
    );
end multiplexer4_1;