_primary.vhd

来自「DMA Directly memory access」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity FIFO2 is
    port(
        clock           : in     vl_logic;
        data            : in     vl_logic_vector(31 downto 0);
        rdreq           : in     vl_logic;
        wrreq           : in     vl_logic;
        empty           : out    vl_logic;
        full            : out    vl_logic;
        q               : out    vl_logic_vector(31 downto 0)
    );
end FIFO2;