_primary.vhd

DDR（双速率）SDRAM控制器参考设计verilog代码

library verilog;
use verilog.vl_types.all;
entity pll1 is
    port(
        inclock         : in     vl_logic;
        locked          : out    vl_logic;
        clock0          : out    vl_logic;
        clock1          : out    vl_logic
    );
end pll1;