虫虫首页| 资源下载| 资源专辑| 精品软件
登录| 注册

您现在的位置是：虫虫下载站 > 资源下载 > VHDL/FPGA/Verilog > DDR SDRAM控制器的VHDL源代码

DDR SDRAM控制器的VHDL源代码

  • 资源大小：130 K
  • 上传时间： 2014-11-01
  • 上传用户：zaindyclg
  • 资源积分：2 下载积分
  • 标      签： SDRAM VHDL DDR 控制器

资 源 简 介

DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.

相 关 资 源

您 可 能 感 兴 趣 的

虫虫下载站版权所有 京ICP备2021023401号-1