_primary.vhd

DDR（双速率）SDRAM控制器参考设计verilog代码

library verilog;
use verilog.vl_types.all;
entity ddr_sdram is
    port(
        clk             : in     vl_logic;
        reset_n         : in     vl_logic;
        addr            : in     vl_logic_vector(21 downto 0);
        cmd             : in     vl_logic_vector(2 downto 0);
        cmdack          : out    vl_logic;
        datain          : in     vl_logic_vector(127 downto 0);
        dataout         : out    vl_logic_vector(127 downto 0);
        dm              : in     vl_logic_vector(15 downto 0);
        sa              : out    vl_logic_vector(11 downto 0);
        ba              : out    vl_logic_vector(1 downto 0);
        cs_n            : out    vl_logic_vector(1 downto 0);
        cke             : out    vl_logic;
        ras_n           : out    vl_logic;
        cas_n           : out    vl_logic;
        we_n            : out    vl_logic;
        dq              : inout  vl_logic_vector(63 downto 0);
        dqm             : out    vl_logic_vector(7 downto 0);
        dqs             : inout  vl_logic_vector(7 downto 0)
    );
end ddr_sdram;