代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/156151/11824215
qsf filtref.qsf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
www.eeworm.com/read/156151/11824249
qsf filtref.qsf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
www.eeworm.com/read/337197/11845803
txt readme.txt
verilog.txt 是加入自动缩进和折叠功能的verilog-98语法文件。已改为L19。
verilog2001 是加入自动缩进和折叠功能的verilog-2001语法文件。已改为L20
wordfile.txt 是加入verilog和veriog2001的文件，替代原安装目录下的wordfile.txt文件即可。
www.eeworm.com/read/344457/11877826
_prj ledwater._prj
insert `timescale 1ns/1ns
include
include ledwater.v
include d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
www.eeworm.com/read/344457/11877886
err automake.err
JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc. All rights reserved.
Scanning d:/Xilinx_WebPACK/data/simprim.lst
Scanning d:/Xilinx_WebPACK/verilog/src/iSE/un
www.eeworm.com/read/344455/11877927
_prj clock._prj
insert `timescale 1ns/1ns
include
include clock.v
include d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
www.eeworm.com/read/344454/11878049
_prj sled._prj
insert `timescale 1ns/1ns
include
include sled.v
include d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
www.eeworm.com/read/344454/11878096
npl 7led.npl
JDF E
// Created by ISE ver 1.0
PROJECT 7led
DESIGN 7led Normal
DEVKIT XC95108 PC84
DEVFAM xc9500
FLOW XST Verilog
MODULE sled.v
MODSTYLE led2 Normal
[STRATEGY-LIST]
Normal=True, 103767358
www.eeworm.com/read/344454/11878154
_prj dled._prj
insert `timescale 1ns/1ns
include
include dled.v
include d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
www.eeworm.com/read/153541/12028875
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity com is
port(
y : out vl_logic_vector(15 downto 0);
a : in vl_logic_vector(15 downto 0);