automake.err

dp_xiliux 的 CPLD Verilog设计实验,流水灯演示.代码测试通过.

JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc.  All rights reserved. 

Scanning    d:/Xilinx_WebPACK/data/simprim.lst
Scanning    d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning    ledwater.v
Writing ledwater.jhd.

JHDPARSE complete -    0 errors,    0 warnings.