filtref.qsf

关于Altera公司FPGA编程的一些常用实例代码.

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:37:58  JANUARY 05, 2004"
set_global_assignment -name LAST_QUARTUS_VERSION 4.0
set_global_assignment -name VERILOG_FILE mult.v
set_global_assignment -name VERILOG_FILE accum.v
set_global_assignment -name SOURCE_FILE hvalues.v
set_global_assignment -name VERILOG_FILE taps.v
set_global_assignment -name VERILOG_FILE state_m.v
set_global_assignment -name VERILOG_FILE acc.v
set_global_assignment -name BDF_FILE filtref.bdf

# Pin & Location Assignments
# ==========================
set_location_assignment MEGALAB_A1 -to "taps:inst"

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name FAMILY APEX20KE
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 1
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 208
set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP
set_global_assignment -name SPEED_DISK_USAGE_TRADEOFF SMART
set_global_assignment -name TOP_LEVEL_ENTITY filtref

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EP20K100EQC208-1"

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT off

# ---------------------
# start ENTITY(filtref)

	# Analysis & Synthesis Assignments
	# ================================
	set_instance_assignment -name APEX20K_TECHNOLOGY_MAPPER "PRODUCT TERM" -to "state_m:inst1"

# end ENTITY(filtref)
# -------------------