7led.npl

dp_xiliux 的 CPLD Verilog设计实验,7个LED演示.代码测试通过.

JDF E
// Created by ISE ver 1.0
PROJECT 7led
DESIGN 7led Normal
DEVKIT XC95108 PC84
DEVFAM xc9500
FLOW XST Verilog
MODULE sled.v
MODSTYLE led2 Normal

[STRATEGY-LIST]
Normal=True, 1037673588