代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/233075/4694907
v verilog.v
// generated by newgenasym Tue Mar 20 14:39:52 2001
module data (gain, outa, outb, vclka, vclkc, vd);
input gain;
output outa;
output outb;
input vclka;
input vclkc;
input [
www.eeworm.com/read/233075/4694911
v verilog.v
`timescale 1ns/1ns
module data (outa, outb, gain, vclka, vclkc, vd );
// generated by HDL Direct 14.20-p006 14-Mar-2002
// on Wed May 01 09:04:34 2002
// from project1_lib/DATA/sch_1
output outa
www.eeworm.com/read/233075/4694926
v verilog.v
// generated by newgenasym Thu Mar 22 13:53:53 2001
module daamp (dq0, dq1, dq2, dq3, dq4, dq5, dq6, dq7, gain, out, vclk, vref);
input dq0;
input dq1;
input dq2;
input dq3;
inp
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v verilog.v
`timescale 1ns/1ns
module daamp (out, dq0, dq1, dq2, dq3, dq4, dq5, dq6, dq7, gain, vclk, vref );
// generated by HDL Direct 14.20-p006 14-Mar-2002
// on Wed May 01 09:04:35 2002
// from project1_li
www.eeworm.com/read/233075/4695006
v verilog.v
`timescale 1ns/1ns
module root ();
// generated by HDL Direct 14.20-p006 14-Mar-2002
// on Wed May 01 09:04:32 2002
// from project1_lib/ROOT/sch_1
// global signal glbl.agnd;
// global signal
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v verilog.v
// generated by newgenasym Thu May 10 13:22:43 2001
module high_speed_ram (ra, rcs0, rcs1, rcs2, rcs3, rd, rwe);
input [15:0] ra;
input rcs0;
input rcs1;
input rcs2;
input rcs3;
www.eeworm.com/read/233075/4695028
v verilog.v
`timescale 1ns/1ns
module high_speed_ram (rd, ra, rcs0, rcs1, rcs2, rcs3, rwe );
// generated by HDL Direct 14.20-p006 14-Mar-2002
// on Wed May 01 09:04:33 2002
// from project1_lib/HIGH_SPEED_RAM/
www.eeworm.com/read/231546/4715400
vim verilog.vim
" Vim syntax file
" Language: Verilog
" Maintainer: Mun Johl
" Last Update: Thu May 3 09:47:51 PDT 2001
" For version 5.x: Clear all syntax items
" For version 6.x: Quit when
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make_verilog
verilog \
../../../bench/verilog/oc8051_tb.v \
../../../bench/verilog/oc8051_xram.v \
../../../bench/verilog/oc8051_uart_test.v \
../../../bench/verilog/oc8051_xrom.v \
../../../rtl/ve
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dump verilog.dump
$date
May 4, 2000 18:30:43
$end
$version
VERILOG-XL 3.0.p001
$end
$timescale
1ns
$end
$scope module system $end
$var wire 1 ! VMA $end
$var wire 1 " R_W $end
$var par