verilog.v

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// generated by newgenasym  Tue Mar 20 14:39:52 2001


module data (gain, outa, outb, vclka, vclkc, vd);
    input gain;
    output outa;
    output outb;
    input vclka;
    input vclkc;
    input [7:0] vd;


    initial
        begin
        end

endmodule