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`timescale 1ns/1ns

module data (outa, outb, gain, vclka, vclkc, vd );
// generated by  HDL Direct 14.20-p006 14-Mar-2002
// on Wed May 01 09:04:34 2002
// from project1_lib/DATA/sch_1

  output  outa;
  output  outb;
  input  gain;
  input  vclka;
  input  vclkc;
  input [7:0] vd;
  // global signal glbl.gnd;

  wire  vref;
  wire  unnamed_1_act574_i1_q0;
  wire  unnamed_1_act574_i1_q1;
  wire  unnamed_1_act574_i1_q2;
  wire  unnamed_1_act574_i1_q3;
  wire  unnamed_1_act574_i1_q4;
  wire  unnamed_1_act574_i1_q5;
  wire  unnamed_1_act574_i1_q6;
  wire  unnamed_1_act574_i1_q7;
  wire  unnamed_1_act574_i2_q0;
  wire  unnamed_1_act574_i2_q1;
  wire  unnamed_1_act574_i2_q2;
  wire  unnamed_1_act574_i2_q3;
  wire  unnamed_1_act574_i2_q4;
  wire  unnamed_1_act574_i2_q5;
  wire  unnamed_1_act574_i2_q6;
  wire  unnamed_1_act574_i2_q7;
  wire  unnamed_1_cap_i11_a;
  wire  unnamed_1_cap_i12_a;
  wire  unnamed_1_cap_i13_a;
  wire  unnamed_1_cap_i14_a;
  wire  unnamed_1_cap_i15_a;
  wire  unnamed_1_cap_i16_a;
  wire  unnamed_1_cap_i17_a;
  wire  unnamed_1_cap_i18_a;

  wire  page1_gain;
  wire  gnd;
  wire  page1_gnd;
  wire  page1_outa;
  wire  page1_outb;
  wire  page1_vclka;
  wire  page1_vclkc;
  wire [7:0] page1_vd;

  assign page1_gain = gain;
  assign gnd = glbl.gnd;
  assign page1_gnd = gnd;
  assign page1_outa = outa;
  assign page1_outb = outb;
  assign page1_vclka = vclka;
  assign page1_vclkc = vclkc;
  assign page1_vd = vd;

  assign gnd  = glbl.gnd;
  assign gnd  = glbl.gnd;
  assign gnd  = glbl.gnd;
  assign gnd  = glbl.gnd;

// begin instances 

  act574 page1_i1  (.clk(vclka),
	.d0(vd[0]),
	.d1(vd[1]),
	.d2(vd[2]),
	.d3(vd[3]),
	.d4(vd[4]),
	.d5(vd[5]),
	.d6(vd[6]),
	.d7(vd[7]),
	.oe(glbl.gnd),
	.q0(unnamed_1_act574_i1_q0),
	.q1(unnamed_1_act574_i1_q1),
	.q2(unnamed_1_act574_i1_q2),
	.q3(unnamed_1_act574_i1_q3),
	.q4(unnamed_1_act574_i1_q4),
	.q5(unnamed_1_act574_i1_q5),
	.q6(unnamed_1_act574_i1_q6),
	.q7(unnamed_1_act574_i1_q7));

  act574 page1_i2  (.clk(vclkc),
	.d0(vd[0]),
	.d1(vd[1]),
	.d2(vd[2]),
	.d3(vd[3]),
	.d4(vd[4]),
	.d5(vd[5]),
	.d6(vd[6]),
	.d7(vd[7]),
	.oe(glbl.gnd),
	.q0(unnamed_1_act574_i2_q0),
	.q1(unnamed_1_act574_i2_q1),
	.q2(unnamed_1_act574_i2_q2),
	.q3(unnamed_1_act574_i2_q3),
	.q4(unnamed_1_act574_i2_q4),
	.q5(unnamed_1_act574_i2_q5),
	.q6(unnamed_1_act574_i2_q6),
	.q7(unnamed_1_act574_i2_q7));

  res page1_i3  (.a(unnamed_1_cap_i11_a),
	.b(vd[7]));

  res page1_i4  (.a(unnamed_1_cap_i12_a),
	.b(vd[6]));

  res page1_i5  (.a(unnamed_1_cap_i13_a),
	.b(vd[5]));

  res page1_i6  (.a(unnamed_1_cap_i14_a),
	.b(vd[4]));

  res page1_i7  (.a(unnamed_1_cap_i15_a),
	.b(vd[3]));

  res page1_i8  (.a(unnamed_1_cap_i16_a),
	.b(vd[2]));

  res page1_i9  (.a(unnamed_1_cap_i17_a),
	.b(vd[1]));

  res page1_i10  (.a(unnamed_1_cap_i18_a),
	.b(vd[0]));

  cap page1_i11  (.a(unnamed_1_cap_i11_a),
	.b(glbl.gnd));

  cap page1_i12  (.a(unnamed_1_cap_i12_a),
	.b(glbl.gnd));

  cap page1_i13  (.a(unnamed_1_cap_i13_a),
	.b(glbl.gnd));

  cap page1_i14  (.a(unnamed_1_cap_i14_a),
	.b(glbl.gnd));

  cap page1_i15  (.a(unnamed_1_cap_i15_a),
	.b(glbl.gnd));

  cap page1_i16  (.a(unnamed_1_cap_i16_a),
	.b(glbl.gnd));

  cap page1_i17  (.a(unnamed_1_cap_i17_a),
	.b(glbl.gnd));

  cap page1_i18  (.a(unnamed_1_cap_i18_a),
	.b(glbl.gnd));

  daamp page1_i56  (.dq0(unnamed_1_act574_i1_q0),
	.dq1(unnamed_1_act574_i1_q1),
	.dq2(unnamed_1_act574_i1_q2),
	.dq3(unnamed_1_act574_i1_q3),
	.dq4(unnamed_1_act574_i1_q4),
	.dq5(unnamed_1_act574_i1_q5),
	.dq6(unnamed_1_act574_i1_q6),
	.dq7(unnamed_1_act574_i1_q7),
	.gain(gain),
	.out(outa),
	.vclk(vclka),
	.vref(vref));

  daamp page1_i57  (.dq0(unnamed_1_act574_i2_q0),
	.dq1(unnamed_1_act574_i2_q1),
	.dq2(unnamed_1_act574_i2_q2),
	.dq3(unnamed_1_act574_i2_q3),
	.dq4(unnamed_1_act574_i2_q4),
	.dq5(unnamed_1_act574_i2_q5),
	.dq6(unnamed_1_act574_i2_q6),
	.dq7(unnamed_1_act574_i2_q7),
	.gain(gain),
	.out(outb),
	.vclk(vclka),
	.vref(vref));

  res page1_i58  (.a(vref),
	.b(glbl.gnd));

endmodule // data(sch_1)