代码搜索:VHDL

找到约 10,000 项符合「VHDL」的源代码

代码结果 10,000
www.eeworm.com/read/355008/10304698

txt 参考.txt

参考testbench教程/教程/writing testbench/16页 1987和1993的区别(文件类型的声明) 93版定义文件,没有in/out之分了,也可参看这里的图片 这里的VHDL textio和上面文件的textio(包含了synopsys的std_logic_textio)第二十六页,write和read的用法,要和这里的《textio用法比较一下》
www.eeworm.com/read/162348/10312092

vhdsim_par receive.vhdsim_par

receive.vhdsim_par -- generated only for ProjNav status tracking Simulation Model Target: Generic_VHDL
www.eeworm.com/read/162348/10312155

vhdsim_par send.vhdsim_par

send.vhdsim_par -- generated only for ProjNav status tracking Simulation Model Target: Generic_VHDL
www.eeworm.com/read/162348/10312366

gfl ex.gfl

# ModelSim : Simulate Behavioral VHDL Model receive_rec_tb_vhd_tb.fdo # ModelSim : Simulate Behavioral VHDL Model vsim.wlf # ModelSim : Simulate Behavioral VHDL Model vsim.wlf # ModelSim : Simul
www.eeworm.com/read/425249/10367124

log modelsim.log

# Reading C:/Libero/Model/tcl/vsim/pref.tcl # do run.do # ** Warning: (vlib-34) Library already exists at "../simulation/postsynth". # Modifying modelsim.ini # Model Technology ModelSim ACTEL vc
www.eeworm.com/read/425249/10367350

prj connect_syn.prj

#add_file options add_file -vhdl "C:/Libero/Synplify/Synplify_81A/lib/proasic/proasicplus.vhd" add_file -vhdl "C:/Actelprj/connect20090223/hdl/fifo_r.vhd" add_file -vhdl "C:/Actelprj/connect2009022
www.eeworm.com/read/424113/10491382

summary dds.map.summary

Analysis & Synthesis Status : Successful - Mon May 28 15:59:37 2007 Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version Revision Name : DDS Top-level Entity Name : DDS_VHDL Family : Stra
www.eeworm.com/read/424113/10491683

summary dds.fit.summary

Fitter Status : Successful - Mon May 28 15:59:51 2007 Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version Revision Name : DDS Top-level Entity Name : DDS_VHDL Family : Stratix Device :
www.eeworm.com/read/160403/10535300

stx lms.stx

Release 6.2i - xst G.31a Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to . CPU : 0.00 / 0.98 s | Elapsed : 0.00 / 1.00 s --> =================================
www.eeworm.com/read/352311/10564545

zsf wed.zsf

E:/tool_stud/vhdl/count.vwf 999998228 1000076469 1076 78241 0 E:/tool_stud/vhdl/db/count.sim.vwf 0 2499969024 974 2499969024 0 count.vwf 0 1000000000 867 1000000000 0