dds.map.summary

经过仿真验证的

Analysis & Synthesis Status : Successful - Mon May 28 15:59:37 2007
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : DDS
Top-level Entity Name : DDS_VHDL
Family : Stratix
Total logic elements : 20
Total pins : 21
Total virtual pins : 0
Total memory bits : 10,240
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0