connect_syn.prj

fpga从FIFO读数据并上传到双口ram中。

#add_file options
add_file -vhdl "C:/Libero/Synplify/Synplify_81A/lib/proasic/proasicplus.vhd"
add_file -vhdl "C:/Actelprj/connect20090223/hdl/fifo_r.vhd"
add_file -vhdl "C:/Actelprj/connect20090223/hdl/dpram_w.vhd"
add_file -vhdl "C:/Actelprj/connect20090223/hdl/connect.vhd"

#device options
set_option -technology PA

#compilation/mapping options
set_option -symbolic_fsm_compiler true

#compilation/mapping options
set_option -frequency 100.000

#simulation options
project -result_file "C:/Actelprj/connect20090223/synthesis/connect.edn"