dds.fit.summary

来自「经过仿真验证的」· SUMMARY 代码 · 共 15 行

Fitter Status : Successful - Mon May 28 15:59:51 2007
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : DDS
Top-level Entity Name : DDS_VHDL
Family : Stratix
Device : EP1S10F484C5
Timing Models : Final
Total logic elements : 20 / 10,570 ( < 1 % )
Total pins : 21 / 336 ( 6 % )
Total virtual pins : 0
Total memory bits : 10,240 / 920,448 ( 1 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )