modelsim.log

fpga从FIFO读数据并上传到双口ram中。

# Reading C:/Libero/Model/tcl/vsim/pref.tcl 
# do run.do 
# ** Warning: (vlib-34) Library already exists at "../simulation/postsynth".
# Modifying modelsim.ini
# Model Technology ModelSim ACTEL vcom 6.0c_p1 Compiler 2005.04 Apr 13 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity dpram_w
# -- Compiling architecture def_arch of dpram_w
# -- Compiling entity fifo_r
# -- Compiling architecture def_arch of fifo_r
# -- Compiling entity connect
# -- Compiling architecture def_arch of connect
# -- Loading entity dpram_w
# -- Loading entity fifo_r
# Model Technology ModelSim ACTEL vcom 6.0c_p1 Compiler 2005.04 Apr 13 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity testbench
# -- Compiling architecture one of testbench
# vsim -t 1ps postsynth.testbench 
# //  ModelSim ACTEL 6.0c_p1 Apr 13 2005 
# //
# //  Copyright Mentor Graphics Corporation 2005
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading C:\Libero\Model\win32acoem/../std.standard
# Loading C:\Libero\Model\win32acoem/../ieee.std_logic_1164(body)
# Loading C:\Libero\Model\win32acoem/../ieee.std_logic_arith(body)
# Loading C:\Libero\Model\win32acoem/../ieee.std_logic_unsigned(body)
# Loading ../simulation/postsynth.testbench(one)
# Loading ../simulation/postsynth.connect(def_arch)
# Loading C:\Libero\Model\win32acoem/../std.textio(body)
# Loading C:\Libero\Model\win32acoem/../ieee.vital_timing(body)
# Loading C:\Libero\Model\win32acoem/../ieee.vital_primitives(body)
# Loading C:/Libero/Model/actel/VHDL/apa.vtables
# Loading C:/Libero/Model/actel/VHDL/apa.ob33ph(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.ib33(vital_act)
# Loading ../simulation/postsynth.dpram_w(def_arch)
# Loading C:/Libero/Model/actel/VHDL/apa.nand3ftt(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.inv(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.mux2h(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.dffc(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.nand2(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.nor3(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.and2(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.ao21ftf(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.xor2(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.aoi21(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.dffs(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.ao21(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.and3(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.and2ft(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.or2(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.and3ftt(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.gnd(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.nor2(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.nand3(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.pwr(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.xor2ft(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.or3(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.nand3fft(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.nor2ft(vital_act)
# Loading ../simulation/postsynth.fifo_r(def_arch)
# Loading C:/Libero/Model/actel/VHDL/apa.ao21ftt(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.or2ft(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.nand2ft(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.or3fft(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.nor3ftt(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.oai21(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.oa21ftt(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.and3fft(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.oa21ttf(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.ao21ttf(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.oa21ftf(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.or3ftt(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.oa21(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.bfr(vital_act)
# Loading C:/Libero/Model/actel/VHDL/apa.gl33(vital_act)
run
quit