ex.gfl

自己在ISE下用VHDL写的UART

# ModelSim : Simulate Behavioral VHDL Model
receive_rec_tb_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
send_send_tb_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
send_send_tb_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
receive_rec_tb_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
receive.spl
__projnav/vhd2spl.err
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
send.spl
__projnav/vhd2spl.err
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
ctrl.spl
__projnav/vhd2spl.err
# Schematic : PDCL (jhdparse)
__projnav/new_top_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/new_top_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/new_top_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/new_top_jhdparse_tcl.rsp
# Schematic : View VHDL Functional Model
new_top.vhf
new_top.cmd_log
# ModelSim : Simulate Behavioral VHDL Model
testbench6.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
new_top.lso
# xst flow : RunXST
new_top.syr
new_top.prj
new_top.sprj
new_top.ana
new_top.stx
new_top.cmd_log
new_top.ngc
new_top.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\sk\iseobject\ex/_ngo
new_top.ngd
new_top_ngdbuild.nav
new_top.bld
.untf
new_top.cmd_log
# Implementation : Map
new_top_map.ncd
new_top.ngm
new_top.pcf
new_top.nc1
new_top.mrp
new_top_map.mrp
new_top.mdf
__projnav/map.log
new_top.cmd_log
MAP_NO_GUIDE_FILE_CPF "new_top"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
new_top.twr
new_top.twx
new_top.tsi
new_top.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
new_top.ncd
new_top.par
new_top.pad
new_top_pad.txt
new_top_pad.csv
new_top.pad_txt
new_top.dly
reportgen.log
new_top.xpi
new_top.grf
new_top.itr
new_top_last_par.ncd
__projnav/par.log
new_top.placed_ncd_tracker
new_top.routed_ncd_tracker
new_top.cmd_log
PAR_NO_GUIDE_FILE_CPF "new_top"
# Implementation : Generate Post-Par Simulation Model
new_top_timesim.vhd
new_top_timesim.sdf
new_top_timesim.sdf
new_top_timesim.vhd
new_top_timesim.nlf
new_top.par_nlf
new_top.vhdsim_par
new_top.cmd_log
__projnav/netgen_par_tcl.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
testbench6.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Generate Programming File
__projnav/new_top_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
new_top.ut
# Generate Programming File
new_top.bgn
new_top.rbt
new_top.ll
new_top.msk
new_top.drc
new_top.nky
new_top.bit
new_top.bin
new_top.isc
new_top.cmd_log
# XST (Creating Lso File) : 
receive.lso
# xst flow : RunXST
receive.syr
receive.prj
receive.sprj
receive.ana
receive.stx
receive.cmd_log
receive.ngc
receive.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\sk\iseobject\ex/_ngo
receive.ngd
receive_ngdbuild.nav
receive.bld
.untf
receive.cmd_log
# Implementation : Map
receive_map.ncd
receive.ngm
receive.pcf
receive.nc1
receive.mrp
receive_map.mrp
receive.mdf
__projnav/map.log
receive.cmd_log
MAP_NO_GUIDE_FILE_CPF "receive"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
receive.twr
receive.twx
receive.tsi
receive.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
receive.ncd
receive.par
receive.pad
receive_pad.txt
receive_pad.csv
receive.pad_txt
receive.dly
reportgen.log
receive.xpi
receive.grf
receive.itr
receive_last_par.ncd
__projnav/par.log
receive.placed_ncd_tracker
receive.routed_ncd_tracker
receive.cmd_log
PAR_NO_GUIDE_FILE_CPF "receive"
# Implementation : Generate Post-Par Simulation Model
receive_timesim.vhd
receive_timesim.sdf
receive_timesim.sdf
receive_timesim.vhd
receive_timesim.nlf
receive.par_nlf
receive.vhdsim_par
receive.cmd_log
__projnav/netgen_par_tcl.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
receive_rec_tb_vhd_tb.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
send.lso
# xst flow : RunXST
send.syr
send.prj
send.sprj
send.ana
send.stx
send.cmd_log
send.ngc
send.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\sk\iseobject\ex/_ngo
send.ngd
send_ngdbuild.nav
send.bld
.untf
send.cmd_log
# Implementation : Map
send_map.ncd
send.ngm
send.pcf
send.nc1
send.mrp
send_map.mrp
send.mdf
__projnav/map.log
send.cmd_log
MAP_NO_GUIDE_FILE_CPF "send"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
send.twr
send.twx
send.tsi
send.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
send.ncd
send.par
send.pad
send_pad.txt
send_pad.csv
send.pad_txt
send.dly
reportgen.log
send.xpi
send.grf
send.itr
send_last_par.ncd
__projnav/par.log
send.placed_ncd_tracker
send.routed_ncd_tracker
send.cmd_log
PAR_NO_GUIDE_FILE_CPF "send"
# Implementation : Generate Post-Par Simulation Model
send_timesim.vhd
send_timesim.sdf
send_timesim.sdf
send_timesim.vhd
send_timesim.nlf
send.par_nlf
send.vhdsim_par
send.cmd_log
__projnav/netgen_par_tcl.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
send_send_tb_vhd_tb.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Post-Place & Route VHDL Model
testbench6.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ModelSim : Simulate Post-Place & Route VHDL Model
send_send_tb_vhd_tb.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ModelSim : Simulate Post-Place & Route VHDL Model
send_send_tb_vhd_tb.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
send_send_tb_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Post-Place & Route VHDL Model
send_send_tb_vhd_tb.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ModelSim : Simulate Post-Place & Route VHDL Model
send_send_tb_vhd_tb.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ModelSim : Simulate Post-Place & Route VHDL Model
send_send_tb_vhd_tb.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\sk\iseobject\ex/_ngo
new_top.ngd
new_top_ngdbuild.nav
new_top.bld
E:/sk/iseobject/ex/sk/u.ucf.untf
new_top.cmd_log
# Implementation : Map
new_top_map.ncd
new_top.ngm
new_top.pcf
new_top.nc1
new_top.mrp
new_top_map.mrp
new_top.mdf
__projnav/map.log
new_top.cmd_log
MAP_NO_GUIDE_FILE_CPF "new_top"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
new_top.twr
new_top.twx
new_top.tsi
new_top.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
new_top.ncd
new_top.par
new_top.pad
new_top_pad.txt
new_top_pad.csv
new_top.pad_txt
new_top.dly
reportgen.log
new_top.xpi
new_top.grf
new_top.itr
new_top_last_par.ncd
__projnav/par.log
new_top.placed_ncd_tracker
new_top.routed_ncd_tracker
new_top.cmd_log
PAR_NO_GUIDE_FILE_CPF "new_top"
# Generate Programming File
__projnav/new_top_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
new_top.ut
# Generate Programming File
new_top.bgn
new_top.rbt
new_top.ll
new_top.msk
new_top.drc
new_top.nky
new_top.bit
new_top.bin
new_top.isc
new_top.cmd_log
# Configure Device (iMPACT)
new_top.prm
new_top.isc
new_top.svf
xilinx.sys
new_top.mcs
new_top.exo
new_top.hex
new_top.tek
new_top.dst
new_top.dst_compressed
new_top.mpm
_impact.cmd
_impact.log
# ModelSim : Simulate Behavioral VHDL Model
send_send_tb_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ModelSim : Simulate Post-Place & Route VHDL Model
send_send_tb_vhd_tb.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Implementation : Generate Post-Par Simulation Model
new_top_timesim.vhd
new_top_timesim.sdf
new_top_timesim.sdf
new_top_timesim.vhd
new_top_timesim.nlf
new_top.par_nlf
new_top.vhdsim_par
new_top.cmd_log
__projnav/netgen_par_tcl.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
testbench6.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Configure Device (iMPACT)
new_top.prm
new_top.isc
new_top.svf
xilinx.sys
new_top.mcs
new_top.exo
new_top.hex
new_top.tek
new_top.dst
new_top.dst_compressed
new_top.mpm
_impact.cmd
_impact.log
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
testbench6.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf