代码搜索：SmartGen
找到约 50 项符合「SmartGen」的源代码
代码结果 50
www.eeworm.com/read/480257/1320589
vhd initcfg_xc.vhd
-------------------------------------------------------------------------------
-- (c) Copyright 2005 Actel Corporation
--
-- name: initcfg_xc.vhd
-- function: SMARTgen IP
-- Rev: 1.4 28Nov05
www.eeworm.com/read/387364/8691192
prj pwm.prj
KEY LIBERO "8.3"
KEY CAPTURE "8.3.0.22"
KEY DEFAULT_IMPORT_LOC "C:\Actelprj\PWM\smartgen\PLL_1"
KEY DEFAULT_OPEN_LOC ""
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family "Fusion"
KEY Vendo
www.eeworm.com/read/17603/740617
prj simple_beep.prj
KEY LIBERO "8.0"
KEY CAPTURE "8.0.3.7"
KEY DEFAULT_IMPORT_LOC "C:\Actelprj\core8051\smartgen\RAM256X8"
KEY DEFAULT_OPEN_LOC ""
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family "Fusion"
KE
www.eeworm.com/read/17720/754723
prj decoder_syn.prj
#add_file options
add_file -verilog "E:/programer_new/Decoder/project/smartgen/Decoder/Decoder.v"
set_option -top_module Decoder
#device options
set_option -technology ProASIC3
set_option -vlog
www.eeworm.com/read/17720/754710
prj decoder_top_syn.prj
#add_file options
add_file -verilog "E:/programer_new/Decoder/project/hdl/KEY.v"
add_file -verilog "E:/programer_new/Decoder/project/smartgen/Decoder/Decoder.v"
add_file -verilog "E:/programer_new/
www.eeworm.com/read/17720/754714
srd decoder_top.srd
%%% protect protected_file
f "noname"; #file 0
f "d:\libero\synplify\synplify_902a2\lib\proasic\proasic3.v"; #file 1
f "e:\programme\decoder\hdl\key.v"; #file 2
f "e:\programme\decoder\smartgen\de
www.eeworm.com/read/17720/754707
srd decoder.srd
%%% protect protected_file
f "noname"; #file 0
f "c:\libero\synplify\synplify_902a2\lib\proasic\proasic3.v"; #file 1
f "e:\easy fpga030\decoder\smartgen\decoder\decoder.v"; #file 2
VNAME 'work.Dec
www.eeworm.com/read/409880/11308438
srd lcd_top.srd
%%% protect protected_file
f "noname"; #file 0
f "d:\actel\libero\libero_v8.4\synplify\synplify_94a1\lib\proasic\fusion.v"; #file 1
f "d:\actelprj\lcd_1602\smartgen\pll_1m\pll_1m.v"; #file 2
f "d:
www.eeworm.com/read/492682/6418927
srd lcd_top.srd
f "noname"; #file 0
f "d:\libero\synplify\synplify_862h\lib\proasic\fusion.v"; #file 1
f "c:\actelprj\yan\lcd_1602\smartgen\pll_1m\pll_1m.v"; #file 2
f "c:\actelprj\yan\lcd_1602\hdl\clock_gen.v"; #
www.eeworm.com/read/409880/11308453
prj lcd_top_syn.prj
#add_file options
add_file -verilog "D:/Actelprj/LCD_1602/smartgen/PLL_1M/PLL_1M.v"
add_file -verilog "D:/Actelprj/LCD_1602/hdl/Clock_Gen.v"
add_file -verilog "D:/Actelprj/LCD_1602/hdl/LCD_Driver.v