decoder_syn.prj

来自「这是Actel 的FPGA的译码器的VHDL源代码。」· PRJ 代码 · 共 18 行

#add_file options
add_file -verilog "E:/programer_new/Decoder/project/smartgen/Decoder/Decoder.v"
set_option -top_module Decoder

#device options
set_option -technology ProASIC3
set_option -vlog_std v2001

#compilation/mapping options
set_option -symbolic_fsm_compiler true

#compilation/mapping options
set_option -frequency 100.000

#simulation options
impl -active "synthesis"
project -result_file "E:/programer_new/Decoder/project/synthesis/Decoder.edn"