decoder_top.srd

这是Actel 的FPGA的译码器的VHDL源代码。

%%% protect protected_file
f "noname"; #file 0
f "d:\libero\synplify\synplify_902a2\lib\proasic\proasic3.v"; #file 1
f "e:\programme\decoder\hdl\key.v"; #file 2
f "e:\programme\decoder\smartgen\decoder\decoder.v"; #file 3
f "e:\programme\decoder\component\work\decoder_top\decoder_top.v"; #file 4
VNAME 'work.Decoder.verilog'; # view id 0
VNAME 'work.decoder_top.verilog'; # view id 1
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