pwm.prj

使用VERILOG 语言产生PWM波。只需要使用处理器或内核直接配置相应的寄存器就可以输出PWM波。

KEY LIBERO "8.3"
KEY CAPTURE "8.3.0.22"
KEY DEFAULT_IMPORT_LOC "C:\Actelprj\PWM\smartgen\PLL_1"
KEY DEFAULT_OPEN_LOC ""
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family "Fusion"
KEY VendorTechnology_Die "IR6X6M2"
KEY VendorTechnology_Package "fg256"
KEY ProjectLocation "d:\我的文档\桌面\fusion  startkit  FPGA平台资料\实验例程\高级实验\PWM\Project\PWM"
KEY SimulationType "VERILOG"
KEY Vendor "Actel"
KEY ActiveRoot "top::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST FileManager
VALUE "<project>\constraint\pwm_top.pdc,pdc"
STATE="utd"
TIME="1192422682"
SIZE="825"
ENDFILE
VALUE "<project>\constraint\top_sdc.sdc,sdc"
STATE="utd"
TIME="1190704748"
SIZE="509"
ENDFILE
VALUE "<project>\designer\impl1\top.adb,adb"
STATE="utd"
TIME="1192430420"
SIZE="462848"
ENDFILE
VALUE "<project>\designer\impl1\top.pdb,pdb"
STATE="utd"
TIME="1192430414"
SIZE="94720"
ENDFILE
VALUE "<project>\designer\impl1\top_ba.sdf,ba_sdf"
STATE="utd"
TIME="1192430386"
SIZE="289198"
ENDFILE
VALUE "<project>\designer\impl1\top_ba.v,ba_hdl"
STATE="utd"
TIME="1192430386"
SIZE="100728"
ENDFILE
VALUE "<project>\designer\impl1\top_fp\top.pro,pro"
STATE="utd"
TIME="1228652052"
SIZE="1481"
ENDFILE
VALUE "<project>\hdl\PWM.v,hdl"
STATE="utd"
TIME="1197084626"
SIZE="2752"
ENDFILE
VALUE "<project>\hdl\PWM_contr.v,hdl"
STATE="utd"
TIME="1197086932"
SIZE="3452"
ENDFILE
VALUE "<project>\hdl\TOP.v,hdl"
STATE="utd"
TIME="1197337056"
SIZE="779"
ENDFILE
VALUE "<project>\simulation\run.do,do"
STATE="utd"
TIME="1190853396"
SIZE="497"
ENDFILE
VALUE "<project>\smartgen\PLL_1\PLL_1.cxf,actgen_cxf"
STATE="utd"
TIME="1190705712"
SIZE="1520"
ENDFILE
VALUE "<project>\smartgen\PLL_1\PLL_1.gen,gen"
STATE="utd"
TIME="1190705710"
SIZE="466"
PARENT="<project>\smartgen\PLL_1\PLL_1.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\PLL_1\PLL_1.log,log"
STATE="utd"
TIME="1190705712"
SIZE="2580"
PARENT="<project>\smartgen\PLL_1\PLL_1.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\smartgen\PLL_1\PLL_1.v,hdl"
STATE="utd"
TIME="1190705712"
SIZE="2488"
PARENT="<project>\smartgen\PLL_1\PLL_1.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\stimulus\control_tbench.btim,btim"
STATE="utd"
TIME="1190704100"
SIZE="5433"
ENDFILE
VALUE "<project>\stimulus\control_tbench.v,tb_hdl"
STATE="utd"
TIME="1190704106"
SIZE="6254"
ENDFILE
VALUE "<project>\stimulus\top_tbench.btim,btim"
STATE="utd"
TIME="1190704514"
SIZE="5197"
ENDFILE
VALUE "<project>\stimulus\top_tbench.v,tb_hdl"
STATE="utd"
TIME="1190704520"
SIZE="6131"
ENDFILE
VALUE "<project>\synthesis\top.edn,syn_edn"
STATE="utd"
TIME="1190855618"
SIZE="311960"
ENDFILE
VALUE "<project>\synthesis\top.v,syn_hdl"
STATE="ood"
TIME="1190704454"
SIZE="93103"
ENDFILE
VALUE "<project>\synthesis\top_drc.rpt,log"
STATE="utd"
TIME="1190705764"
SIZE="6813"
ENDFILE
VALUE "<project>\synthesis\top_sdc.sdc,syn_sdc"
STATE="utd"
TIME="1190855618"
SIZE="310"
ENDFILE
VALUE "<project>\viewdraw\sym\control.1,sym"
STATE="utd"
TIME="1197337074"
SIZE="844"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "control::work"
FILE "<project>\hdl\PWM_contr.v,hdl"
LIST AssociatedStimulus
VALUE "<project>\stimulus\control_tbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
ideSTIMULUSEDITOR=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "top::work"
FILE "<project>\hdl\TOP.v,hdl"
LIST AssociatedStimulus
VALUE "<project>\stimulus\top_tbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Layout
ideSTIMULUS=StateSuccess
ideSTIMULUSEDITOR=StateSuccess
ideSYNTHESIS(<project>\synthesis\top.edn,syn_edn)=StateSuccess
ideDESIGNER(<project>\designer\impl1\top.adb,adb)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\top.edn,syn_edn"
VALUE "<project>\synthesis\top_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\top.v,syn_hdl"
VALUE "<project>\phy_synthesis\top_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\top_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\top_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\top_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\top_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\top.adb,adb"
VALUE "<project>\designer\impl1\top.prb,prb"
VALUE "<project>\designer\impl1\top.stp,stp"
VALUE "<project>\designer\impl1\top_fp\top.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
LIST top
VALUE "<project>\stimulus\top_tbench.v,tb_hdl"
ENDLIST
LIST control
VALUE "<project>\stimulus\control_tbench.v,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DumpVCD=false
VCDFileName=power.vcd
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
UpdateViewDrawIni=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
GenerateHDLFromSchematic=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
Type=CoreConfigurator
Profile=CoreConsole
Tool=CoreConsole v1.3 or later
Location=D:\CoreConsole_v1.4\bin\CoreConsole.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Synthesis
Profile=Synplify
Tool=Synplify
Location=D:\Libero\Synplify\Synplify_902A2\bin\Synplify.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Simulation
Profile=ModelSim
Tool=ModelSim
Location=D:\Libero\Model\win32acoem\modelsim.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Stimulus
Profile=WFL
Tool=WFL
Location=D:\Libero\WFL\bin\syncad.exe
AdditionalParameter=-pwflite
Batch=false
EndProfile
Type=PhySynthesis
Profile=
Tool=
Location=
AdditionalParameter=
Batch=false
EndProfile
Type=Program
Profile=FlashPro
Tool=FlashPro
Location=D:\Libero\FlashPro\bin\FlashPro.exe
AdditionalParameter=
Batch=false
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "control::work"
LIST Impl1
ideSTIMULUS=StateSuccess
ideSTIMULUSEDITOR=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "top::work"
LIST Impl1
LiberoState=Post_Layout
ideSTIMULUS=StateSuccess
ideSTIMULUSEDITOR=StateSuccess
ideSYNTHESIS(<project>\synthesis\top.edn,syn_edn)=StateSuccess
ideDESIGNER(<project>\designer\impl1\top.adb,adb)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\top.edn,syn_edn"
VALUE "<project>\synthesis\top_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\top.v,syn_hdl"
VALUE "<project>\phy_synthesis\top_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\top_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\top_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\top_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\top_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\top.adb,adb"
VALUE "<project>\designer\impl1\top.prb,prb"
VALUE "<project>\designer\impl1\top.stp,stp"
VALUE "<project>\designer\impl1\top_fp\top.pro,pro"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
DESIGNFLOW:
FILE:<project>\hdl\PWM_contr.v,hdl
FILE:<project>\hdl\TOP.v,hdl
FILE:<project>\hdl\PWM.v,hdl
ACTIVE_VIEW:2
ENDLIST