decoder_top_syn.prj

这是Actel 的FPGA的译码器的VHDL源代码。

#add_file options
add_file -verilog "E:/programer_new/Decoder/project/hdl/KEY.v"
add_file -verilog "E:/programer_new/Decoder/project/smartgen/Decoder/Decoder.v"
add_file -verilog "E:/programer_new/Decoder/project/component/work/decoder_top/decoder_top.v"
set_option -top_module decoder_top

#device options
set_option -technology ProASIC3
set_option -vlog_std v2001

#compilation/mapping options
set_option -symbolic_fsm_compiler true

#compilation/mapping options
set_option -frequency 100.000

#simulation options
impl -active "synthesis"
project -result_file "E:/programer_new/Decoder/project/synthesis/decoder_top.edn"