代码搜索：Numeric
找到约 7,754 项符合「Numeric」的源代码
代码结果 7,754
www.eeworm.com/read/363304/9960331
vhd count_distance.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity count_distance is
port( clkin : in std_logic;
di
www.eeworm.com/read/363304/9960344
vhd texitype_select.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity texitype_select is
port( clk : in std_logic;
sta
www.eeworm.com/read/162264/10321594
vhd mult3.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mult3 is
generic(a1:natural;
b1:natural;
q1:natural);
port(clk:in std_logic;
resetn:in std_
www.eeworm.com/read/160403/10535368
vhd testmux.vhd
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE WORK.PCK_multiplier.ALL;
ENTITY test_test_vhd_tb IS
END test_test_vhd_tb;
ARCHITECTURE behavior OF test_test_vh
www.eeworm.com/read/350014/10776246
vhd sinetest4ksample1ksignal.vhd
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
entity SineTest4KSample1KSignal is
end entity SineTest4KSample1KSignal;
architecture OneK
www.eeworm.com/read/468104/6999812
bak datasource.vhd.bak
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
--use WORK.addreload.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY datasource IS
port(
clk : i
www.eeworm.com/read/468104/6999964
vhd datasource.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
--use WORK.addreload.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY datasource IS
port(
clk : i
www.eeworm.com/read/170130/7102965
vhf detector.vhf
-- VHDL model created from detector.sch - Fri Jun 16 15:52:05 2006
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.V
www.eeworm.com/read/210238/7127413
vhf mimasuo.vhf
-- VHDL model created from mimasuo.sch - Thu Apr 19 19:18:50 2007
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vc
www.eeworm.com/read/448525/7532145
vhd databuffer.vhd
library ieee;
use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity DATABUFFER is
port(
CLOCK_50: IN STD_LOGIC;
SW: in std_logic_vector(9 downto 0);